Encoding and decoding are performed in various known ways in a variety iof applications, such as in computer systems. For example, a conventional content addressable memory (CAM) can include an address encoder that provides address codes in response to priority encoder signals that indicate locations in a CAM.
FIG. 1 shows features of conventional address encoder 10, which illustratively receives location signals L0 through L15 on input lines 12 and provides four-bit address codes A0 through A3 on output lines 14. For proper operation, the location signals on input lines 12 are uncoded parallel signals, with at most one of location bits L0 through L15 on input lines 12 asserted at any time, while encoder 10 can assert any combination of address bits A0 through A3 on output lines 14, depending on which of location bits L0 through L15 is asserted. Each of input lines 12 is connected to the gate of each of a set of between zero and four transistors, and each transistor pulls down one of output lines 14 when turned on by an asserted location bit at its gate. For example, when location signal L13 on input line 16 is asserted, transistors 20, 22, and 24 are turned on, pulling down output lines 30, 32, and 34, respectively, asserting address bits A0, A2, and A3.
Although address encoder 10 is relatively simple, it has certain disadvantageous characteristics. For example, the series of eight transistors along output line 30 limits layout flexibility—encoder 10 must be laid out with techniques that allow a series of eight transistors connected to consecutive input lines along an output line. As the number of input lines increases, this problem becomes more pronounced, because an encoder with 32 input lines would have a series of sixteen transistors along an output line.
It would be advantageous to have more flexible techniques for signal conversion, such as between uncoded parallel signals and codes.